S235    9-2-10

OEES 235 Digital II
Bruce McDowell
e-mail address and phone
Fall 2010

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Syllabus

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Homework, Lab Work, & Class Exercises
H = homework, L = lab, CE = class exercise

Type Assignment
No.

Date Assigned

Date Due Points  Description
L GH27-13 8-19 8-26 20 Use the ispLever schematic editor to draw a circuit with an AND gate, OR gate, and a D flip-flop. Directions.
L GI5-10 8-19 8-26 20 Simulate the circuit from GH27-13. Directions.
L GH29-12 8-? 8-29 25 Convert a D flip-flop into a JK flip-flop.
L JI02-27 9-02 9-09 15 30 Forward, stop, reverse
L IH25-25 20
Truth table; Karnaugh/Vietch; equation; gates; Lever simulation.
Truth table => OR gate
L GI19_13 20 Counter with enable. Directions.
L GI21-13 20 Tone translator up-counter. Directions
L GI26-13 Timing signals (tone translator) Directions
L GJ01-10 Improved timing signals. Directions
L GJ05-09 20 Octave shifter and blocks (tone translator). Directions.
L II28-27 50 Four inputs and two motors. Directions
L GJ12-09 15 Square wave generator (tone translator). Directions
L GJ16-18 15 Count and stop circuit. Directions.
L GJ21-08 20 Shift to highest octave. Directions.
CE GJ22-12 10 Octave-Counter Adder. Directions.
L GJ26-12 20 Octave counter. Directions
L GJ15-15 20 Octave shifter, version 2. Directions.
L GK02-15 20 Timing Signal Generator, Version 4. Directions.
CE GK12-08 15 Note to 4-bit period converter Directions
L GK12-16 30 Note to 12-bit period converter
Directions

Extra Credit

Assignment
No.

Due Date

 
     

Reference
Reference Material for Lever Macros
"Data sheets" for gates, flip-flops, counters, etc. 
OEES235 Custom Macros
Hexadecimal Numbers