gj24-12 Square Wave Generator, Version 2
20 points

OEES 235

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Legend
  • LATCH_OUT_PER = Latch output period into four-bit latch.
  • QSH0 - QSH3 = Outputs from octave shifter (which specifies how long the square wave's period should be).
  • START = Start the count-and-stop cycle. The input to this pin needs to be one clock-period wide.
  • ENBL = Enable. This line goes high for the number of clock pulses specified on D0 - D3 of the Count and Stop block.
  • SWOUT = Square wave out. Actual square wave that will be amplified and sent to speaker.
  • LDSWCNT = Load Square wave counter.



The previous version of the square-wave generator (gj12-09) was a bit complicated, and had some problems that aren't readily apparent. Version 2, uses the Count and Stop block to simplify the circuit. Version 2 also has the latches needed to hold the number from the octave shifter.

Remember that the Count and Stop block operates as follows:
  1. A binary number is placed on it's inputs (D0 - D3).
  2. A pulse one clock-period wide is sent to the START input.
  3. The ENBL output goes high for the number of clock pulses that was specified on D0 - D3.
I25 in the schematic above is a four-bit latch. It's basically four D flip-flops, with their clock inputs tied together. When LOAD_OUT_PER goes high, whatever signals are present on D0 - D3 are latched into the four flip-flops and made available to the adder.

I38 is a 4-bit half-adder. It's being used to subtract one from the number coming from the octave shifter. The nature of the square wave generator circuit is to give a square wave that's one pulse too wide. Subtracting one solves this problem. Notice that B3 - B0 are tied high. In other words, 1111 is added to whatever number is present on A3 - A0. The number 1111 is the two's complement of 1. In other words, it's -1.

Here are descriptions of what's needed for inputs to the two flip-flops and to the Count and Stop block:
  • The JK flip-flop should toggle every time ENBL goes from low to high.
  • LDSWCNT should go high for one clock period when ENBL has just gone low. You'll need to use the D flip-flop to accomplish this.
    • In other words, LDSWCNT should go high when ENBL is low but the output of the D flip-flop is still high.
  • The START input to the Count and Stop block should go high when LATCH_OUT_PER is high or when LDSWCNT is high.
    • LATCH_OUT_PER accomplishes two tasks: It loads OSH0 - OSH3 into the 4-bit latch, and it starts the Count and Stop block if it is not already running.
Right click here to get the partial schematic as shown above.
Right click here to get the schematic for the Count and Stop block.
Right click here to get the test vector file.

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