Revised 10-29

gj26-12 Octave Counter
20 points

OEES 235

Back to Main Page

 
 
Legend
OCTUP Octave up. From Increase Octave button. OCQ2 - OCQ0 Octave counter outputs, unadjusted.
OCTDN Octave down. From Decrease Octave button. OCTCNTR2 - OCTCNTR0 Octave counter outputs, adjusted so that negative numbers have LEFT_RIGHT = 1 and a regular (non-two's complement) number.
OCTMID Octave middle. From Middle Octave button LEFT_RIGHT If high, tell shift-register to shift left. If low, shift right. (The outputs of this schematic will go to another circuit that contains the actual shift register.)
EN_OCT_CNTR Enable Octave counter



Right click for:
Partial schematic.
Test vector.

The circuitry in this schematic will produce signals (OCTCNTR2 - OCTCNTR0 and LEFT_RIGHT) that tell the octave-shifting shift-register how many positions to shift the period number, and which direction to shift them (left or right).

The inputs to the schematic above (except for CLK) will come from push buttons.

Your job is to add the missing parts to the schematic.

Tips:
  • The purpose of the two D flip-flops on the left is to allow creation of signals that go high only for one clock period when OCTUP or OCTDN go high (probably for more than one clock period).
  • The component in the middle of the schematic is an up/down counter.
    • When OCTUP goes high, this counter should count up by one.
    • When OCTDN goes high, it should count down by one.
    • When OCTMID goes high, the number 00012 should be loaded into the counter. (This corrects for the fact that the Up Counter produces a period value that's one octave too low.)
  • The EN input to the counter should go high under the following conditions: OCTUP has just gone high, or OCTDN has just gone high.
    • In other words, if OCTUP is high (for example), and the D flip-flip connected to OCTUP is still low, we know that the OCTUP signal has just gone low high.
  • If you review what has been said above, you can see what condition should make the LD input go high, and what condition should make the DNUP input go high.
    • Notice that the UP in DNUP has a bar over it.
  • The exclusive OR gates and adder at the right of the schematic are the same as what we examined in class exercise gj22-12.
    • Their purpose is to take the 2's complement of the octave counter's number if the counter contains a negative number (in other words, if the high order bit, Q3, of the counter is high).
Looking at the waveforms, notice the following:
  • When OCTMID goes high, 00012 is loaded into the counter.
  • Even though OCTUP goes high for more than one clock period, the counter only counts up by one each time.
  • Each time OCTDN goes high, counter counts down by one.
  • After the third OCTDN pulse, the counter has reached zero.
  • The fourth OCTDN pulse causes the counter to count down by one, resulting in 1112 , which is the two's complement of 0012. In other words, the counter contains -1.
  • The fifth OCTDN pulse again causes the counter to count down by one, resulting in 1102 , which is the two's complement of 0102 (decimal 2). In other words, the counter now contains -2.
  • Notice also that when OCTDN goes high for the fourth time, OCQ2 - OCQ0 contains negative numbers in two's complement form, and OCTCNTR2 - OCTCNTR0 contains the regular (non-two's complement) version of the number.
    • The LEFT_RIGHT signal serves as a sign bit, with a high meaning that the number in OCTCNTR2 - OCTCNTR0 is a negative one.
Back to Main Page
1